I'd like to abuse category 6 UTP by using it to carry I²C traffic. I used an AVR M-Tester to measure the parasitic capacitance of the different cores in a 30 m length of CAT6 cable.
A | B | Capacitance/pF |
---|---|---|
White/Green | Green | 1703 |
" | White/Orange | 869 |
" | Blue | 770 |
" | White/Blue | 769 |
" | Orange | 869 |
" | White/Brown | 879 |
" | Brown | 872 |
White/Orange | Orange | 1550 |
Blue | White/Blue | 1606 |
White/Brown | Brown | 1565 |
Of course it makes sense that the pairs have higher parasitic capacitance since the conductors are closer to each other, but it's useful to know when choosing the wiring scheme. The scheme in use is:
Position | Use |
---|---|
1 | GND |
2 | +5V |
3 | SCL |
4 | SDA |
5 | GND |
6 | +12V |
7 | GND |
8 | +12V |
It might be useful (or at least not detrimental) to have capacitance across the power supply lines.
Would it be better to pair SDA with SCL, or to pair each with either GND or +5V?
I wonder whether the capacitance of a pair is correlated to its twist rate.
I²C specifies a limit of 400 pF for bus capacitance.
The bus capacitance rises as devices are added.
The parasitic capacitance of the bus lines affects the slew rate of the signals, which limits the maximum frequency at which changes can reliably be discerned.